This invention relates to a dynamic random access memory (hereinafter referred to as a dynamic RAM), more particularly to the word-line reset structure of such a dynamic RAM.
A dynamic RAM comprises a matrix of memory cells having storage capacitors and transfer gate transistors. The gate electrodes of the transfer gate transistors are connected to word lines running in the row direction of the matrix, their source electrodes are connected to bit lines running in the column direction, and their drain electrodes are connected to storage nodes. The storage nodes are in turn connected to the storage capacitors, in which bit data are stored as levels of charge. A memory cell is read by selecting its word line and sensing the voltage on its bit line, after which the memory cell is refreshed to restore the charge level in the storage capacitor. Even when data output is not required, the memory cell must be refreshed periodically to compensate for charge leakage.
After a memory cell is read or refreshed, its bit line must be precharged to a certain potential level to prepare for the next access or refresh cycle. All word lines must be clamped to the ground potential level at this time, so that the charging of the bit line will not produce unwanted activation of word lines via the parasitic capacitance between the word and bit lines.
A prior-art scheme for clamping the word lines provides terminating NMOS field-effect transistors, the source electrodes of which are connected to ground and the drain electrodes of which are connected to respective word lines. The gate electrodes of all these NMOS transistors are connected to a word reset signal line. During precharging of the bit lines, the word reset signal is active and all word lines are clamped to ground level. At other times the word reset signal is inactive and the word lines are disconnected from ground.
One problem of this scheme is that the circuit that generates the word reset signal must drive a large number of NMOS transistors, in addition to charging and discharging the parasitic capacitance of the word reset signal line. Another problem is that all the word lines are switched on and off in every memory cycle, requiring current to charge and discharge the parasitic capacitances of all the word lines. Owing to these two problems, a large charge-discharge current is consumed in each memory cycle, increasing the power dissipation of the dynamic RAM.
Yet another problem is that, except during precharging, both selected an non-selected word lines are disconnected from ground. This allows noise to occur on non-selected word lines, which tends to increase the escape of charge from memory cells and reduces the data retention margin.